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========================================================================= Date: Fri, 10 Apr 1998 14:15:21 -0700
Reply-To: "CYHIST Community Memory: Discussion list on the History of
Cyberspace" <CYHIST@MAELSTROM.STJOHNS.EDU> Sender: "CYHIST Community Memory: Discussion list on the History of
Cyberspace" <CYHIST@MAELSTROM.STJOHNS.EDU> From: Stan Mazor <stan.mazor@BEASYS.COM>
Subject: Summer Novel (Adder circuit)
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______________________________________________________________________
Community Memory: Discussion List on the History of Cyberspace ______________________________________________________________________
A novel summer (addder) built with 8 pass transistors Stan Mazor 4-98 The following novel adder circuit was shown to me by engineer Sam Schwartz which has its origin in relay logic. It is a fine example of routing logic and of how an adder "works".
Binary Half-Adder
A half adder is an exclusive-or function; the truth table for the sum of A and B is:
A
0 1
----------
B |
0 | 0 1
1 | 1 0
Binary Full Adder
A binary full adder consists of two cascaded half-adders. Binary full adders allow for multi-bit addition and have a carry-in, which is the carry-out from the previous (lower stage)addition. The sum S of : A, B, and C the carry-in is given by the equation: S =A v B v C which requires 2 exclusive-or (v) hardware "gates". or S(A,B,C) = (~A~BC) + (~AB~C) + (A~B~C) + (ABC) (~ is not)
The truth table for S is shown (left)and is the odd parity function.
A B C S A novel routing circuit using 8 pass transistors below 0 0 0 0 has a path from 1-> S for each of the 4 terms of S. 0 0 1 1 S term Routing
0 1 0 1 -------+-------- (ABC) 1->A->C->B->S
0 1 1 0 ~A | B | A | (~AB~C) 1->~A->~C->B->S
1 0 0 1 +--C----+- ~C---+ A~B~C) 1->~B ->~C->A->S
1 0 1 0 A | ~B | ~A | (~A~BC) 1->~B->->C->~A->S
1 1 0 0 -------+--------
1 1 1 1 1
An equation to generate the carry out (C') which is the C input in the next higher bit stage is: C' = (A& B) + (A&C) + (B&C) or simply written as = AB + AC + BC (+ is an or, & is and)
The routing circuit (exercise) is not shown here.
>thx. stan
>------------------------------------------------- Stanley Mazor 408-542-4120 phone
>Training Department 408-542-4110 fax
>BEA Systems smazor@beasys.com
>385 Moffett Park Dr. Enterprise Middleware
>Sunnyvale, Ca. 94089-1208
>
>
------------------------------------------------- Stanley Mazor 408-542-4120 phone
Training Department 408-542-4110 fax
BEA Systems smazor@beasys.com
385 Moffett Park Dr. Enterprise Middleware
Sunnyvale, Ca. 94089-1208
______________________________________________________________________
Reply-To: "CYHIST Community Memory: Discussion list on the History of
Cyberspace" <CYHIST@MAELSTROM.STJOHNS.EDU> Sender: "CYHIST Community Memory: Discussion list on the History of
Cyberspace" <CYHIST@MAELSTROM.STJOHNS.EDU> From: Stan Mazor <stan.mazor@BEASYS.COM>
Subject: Summer Novel (Adder circuit)
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
______________________________________________________________________
Community Memory: Discussion List on the History of Cyberspace ______________________________________________________________________
A novel summer (addder) built with 8 pass transistors Stan Mazor 4-98 The following novel adder circuit was shown to me by engineer Sam Schwartz which has its origin in relay logic. It is a fine example of routing logic and of how an adder "works".
Binary Half-Adder
A half adder is an exclusive-or function; the truth table for the sum of A and B is:
A
0 1
----------
B |
0 | 0 1
1 | 1 0
Binary Full Adder
A binary full adder consists of two cascaded half-adders. Binary full adders allow for multi-bit addition and have a carry-in, which is the carry-out from the previous (lower stage)addition. The sum S of : A, B, and C the carry-in is given by the equation: S =A v B v C which requires 2 exclusive-or (v) hardware "gates". or S(A,B,C) = (~A~BC) + (~AB~C) + (A~B~C) + (ABC) (~ is not)
The truth table for S is shown (left)and is the odd parity function.
A B C S A novel routing circuit using 8 pass transistors below 0 0 0 0 has a path from 1-> S for each of the 4 terms of S. 0 0 1 1 S term Routing
0 1 0 1 -------+-------- (ABC) 1->A->C->B->S
0 1 1 0 ~A | B | A | (~AB~C) 1->~A->~C->B->S
1 0 0 1 +--C----+- ~C---+ A~B~C) 1->~B ->~C->A->S
1 0 1 0 A | ~B | ~A | (~A~BC) 1->~B->->C->~A->S
1 1 0 0 -------+--------
1 1 1 1 1
An equation to generate the carry out (C') which is the C input in the next higher bit stage is: C' = (A& B) + (A&C) + (B&C) or simply written as = AB + AC + BC (+ is an or, & is and)
The routing circuit (exercise) is not shown here.
>thx. stan
>------------------------------------------------- Stanley Mazor 408-542-4120 phone
>Training Department 408-542-4110 fax
>BEA Systems smazor@beasys.com
>385 Moffett Park Dr. Enterprise Middleware
>Sunnyvale, Ca. 94089-1208
>
>
------------------------------------------------- Stanley Mazor 408-542-4120 phone
Training Department 408-542-4110 fax
BEA Systems smazor@beasys.com
385 Moffett Park Dr. Enterprise Middleware
Sunnyvale, Ca. 94089-1208
______________________________________________________________________
