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Cyhist Apr. 2 1998 b
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========================================================================= Date: Thu, 2 Apr 1998 16:43:04 -0800
Reply-To: "CYHIST Community Memory: Discussion list on the History of
Cyberspace" <CYHIST@MAELSTROM.STJOHNS.EDU> Sender: "CYHIST Community Memory: Discussion list on the History of
Cyberspace" <CYHIST@MAELSTROM.STJOHNS.EDU> From: Stan Mazor <stan.mazor@BEASYS.COM>
Subject: Intel 8080 history
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______________________________________________________________________
Community Memory: Discussion List on the History of Cyberspace ______________________________________________________________________
I was a Symbol computer designer at Fairchild 66-69. I worked for Ted Hoff at Intel as an Applications Engineer starting 9/9/69 and worked on the development of intel MCS-4, MCS-8, 8080 and 8086. After our announcement of the first 2 microcomputers, I supported customers, wrote articles, and gave papers on microcomputer usage. I collected and analyzed suggestions, criticisms and problems with 8008, during its first years of usage 1972-1973. I also spoke a few times by phone with Harry Pyle at Datapoint to see what improvements he was making in their next Datapoint CPU design.
During this time Intel developed their N-MOS process (MCS-4, MCS-8 were P-MOS). I worked on the 8080 architecture and summarize some of the details here. I specifically dispute the conjecture that Intel considered doing PDP-11 on a chip. I did visit DEC to consider a PDP-8 (12-bit) chip. These are my recollections as of 3/98.
1. Faggin proposed to Vasdasz that we re-run the 8008
masks in the N-MOS process to get a faster chip. Vasdasz approved the project budget. Faggin did a quick study concluding that the transistor masks wouldn't work because of wrong(Z/L) ratio scaling. Therefore we needed a new mask set; Vasdasz agreed.
2. Faggin and I reckoned we would "fix a few problems"
when we did the new design. Note we only had approval for a revised 8008 mask set !! not for a new architecture.
3. I wrote 3 specifications called "Super-8", dubbed for the
then new 8mm film standard. Each one was more agressive but we settled finally on my intermediate proposal which was pretty compatible with the 8008 but had a number of features well documented in our IEEE articles on the 8080.
4. Around 1972 I vi
sited DEC as both Ted and I were avid PDP-8
users to consider doing a PDP-8 (12 bit) CPU chip. DEC only needed 5k CPU's per year and that was only 1 weeks chip production. But mainly...!!!the PDP-8 was not really suitable for control programming with ROM because subroutine return addresses needed to be stored in the program memory (can't write to ROM). So I rejected doing the PDP-8 as a single chip CPU.
5. RCA later built the PDP-8 as a COSMAC chip which I believed
(by prior analysis) to be a mistake.
6. Ted and I bought a PDP0-10 from John Lange the DEC PDP-10
product line manager in order to run the transient analysis program I had written in Fortran under Ted's directions. We had pretty good connections to DEC for this reason and also reason #4 above.
7. I know of NO CONTACT or consideration to do a PDP-11 on a chip
in the time period 1972-1974 at Intel:
a. chip size was not feasible
b. we were only pursuing upwardly compatible products c. our contact was with PDP-8 and PDP-10 groups I seriously doubt the claim that Intel contacted DEC about building a PDP-1l chip during that time.
8. Regarding my 3rd proposal for Super-8, it is noteworthy that
the idea was to utilize the 16-bit address field as follows:
1 bit index register (H/L)
1 bit indirect indicator
14 bit displacement
8008 compatability was given using a zero displacement and indexed by HL. This was considered a poor choice:
a. 8008 compatability would require prior 1 byte
HL indirect instructions to use 3 bytes. b. It would require a 16-bit addition operation during
instruction decode which was too costly.
9. Final choice of 8080 allowed for 16 bit addition of
HL and DE which was more general than using adder for address calculation. We could code a 16-bit multiply and a 16-bit divide using the primitive 16-bit add within an inner loop. Although not as elegant, we considered 8080 final choice to be cheaper and more flexible.
10. 8080 chip design was done by Shima who joined Intel from Busicom.
Faggin supervised all of this work and was in charge of the "small machine" development. Shima and I consulted on the instruction set and made some final compromises at implementation time, finally leaving 12 instructions unused (see my history article in IEEE proceedings for more details on this).
11. Intel filed for a patent on the 8080 (Shima, Faggin, Mazor)
a. the patent covers specific "tricks" used within the
8080 which we believed to be real inventions. b. one of these inventions was given by Ted and is the trick
for swapping the contents of registers DE and HL which you do by toggling a labelling flip/flop.
12. Ted and I had proposed a much simpler chip after our MCS-4
proposal for Busicom. This chip was called the 4005 and was to be done jointly with our Canadian parnter MIL. This chip was never built. It was to have had only 2 address registers the PC and the DataPointer. These 2 registers would be swapped to do subroutine call and save. The swap was to be done by toggling a labelling flip/flop.
13. IBM has the patent on register swap using F/F. thx. stan
------------------------------------------------- Stanley Mazor 408-542-4120 phone
Training Department 408-542-4110 fax
BEA Systems smazor@beasys.com
385 Moffett Park Dr. Enterprise Middleware
Sunnyvale, Ca. 94089-1208
______________________________________________________________________
Reply-To: "CYHIST Community Memory: Discussion list on the History of
Cyberspace" <CYHIST@MAELSTROM.STJOHNS.EDU> Sender: "CYHIST Community Memory: Discussion list on the History of
Cyberspace" <CYHIST@MAELSTROM.STJOHNS.EDU> From: Stan Mazor <stan.mazor@BEASYS.COM>
Subject: Intel 8080 history
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
______________________________________________________________________
Community Memory: Discussion List on the History of Cyberspace ______________________________________________________________________
I was a Symbol computer designer at Fairchild 66-69. I worked for Ted Hoff at Intel as an Applications Engineer starting 9/9/69 and worked on the development of intel MCS-4, MCS-8, 8080 and 8086. After our announcement of the first 2 microcomputers, I supported customers, wrote articles, and gave papers on microcomputer usage. I collected and analyzed suggestions, criticisms and problems with 8008, during its first years of usage 1972-1973. I also spoke a few times by phone with Harry Pyle at Datapoint to see what improvements he was making in their next Datapoint CPU design.
During this time Intel developed their N-MOS process (MCS-4, MCS-8 were P-MOS). I worked on the 8080 architecture and summarize some of the details here. I specifically dispute the conjecture that Intel considered doing PDP-11 on a chip. I did visit DEC to consider a PDP-8 (12-bit) chip. These are my recollections as of 3/98.
1. Faggin proposed to Vasdasz that we re-run the 8008
masks in the N-MOS process to get a faster chip. Vasdasz approved the project budget. Faggin did a quick study concluding that the transistor masks wouldn't work because of wrong(Z/L) ratio scaling. Therefore we needed a new mask set; Vasdasz agreed.
2. Faggin and I reckoned we would "fix a few problems"
when we did the new design. Note we only had approval for a revised 8008 mask set !! not for a new architecture.
3. I wrote 3 specifications called "Super-8", dubbed for the
then new 8mm film standard. Each one was more agressive but we settled finally on my intermediate proposal which was pretty compatible with the 8008 but had a number of features well documented in our IEEE articles on the 8080.
4. Around 1972 I vi
sited DEC as both Ted and I were avid PDP-8
users to consider doing a PDP-8 (12 bit) CPU chip. DEC only needed 5k CPU's per year and that was only 1 weeks chip production. But mainly...!!!the PDP-8 was not really suitable for control programming with ROM because subroutine return addresses needed to be stored in the program memory (can't write to ROM). So I rejected doing the PDP-8 as a single chip CPU.
5. RCA later built the PDP-8 as a COSMAC chip which I believed
(by prior analysis) to be a mistake.
6. Ted and I bought a PDP0-10 from John Lange the DEC PDP-10
product line manager in order to run the transient analysis program I had written in Fortran under Ted's directions. We had pretty good connections to DEC for this reason and also reason #4 above.
7. I know of NO CONTACT or consideration to do a PDP-11 on a chip
in the time period 1972-1974 at Intel:
a. chip size was not feasible
b. we were only pursuing upwardly compatible products c. our contact was with PDP-8 and PDP-10 groups I seriously doubt the claim that Intel contacted DEC about building a PDP-1l chip during that time.
8. Regarding my 3rd proposal for Super-8, it is noteworthy that
the idea was to utilize the 16-bit address field as follows:
1 bit index register (H/L)
1 bit indirect indicator
14 bit displacement
8008 compatability was given using a zero displacement and indexed by HL. This was considered a poor choice:
a. 8008 compatability would require prior 1 byte
HL indirect instructions to use 3 bytes. b. It would require a 16-bit addition operation during
instruction decode which was too costly.
9. Final choice of 8080 allowed for 16 bit addition of
HL and DE which was more general than using adder for address calculation. We could code a 16-bit multiply and a 16-bit divide using the primitive 16-bit add within an inner loop. Although not as elegant, we considered 8080 final choice to be cheaper and more flexible.
10. 8080 chip design was done by Shima who joined Intel from Busicom.
Faggin supervised all of this work and was in charge of the "small machine" development. Shima and I consulted on the instruction set and made some final compromises at implementation time, finally leaving 12 instructions unused (see my history article in IEEE proceedings for more details on this).
11. Intel filed for a patent on the 8080 (Shima, Faggin, Mazor)
a. the patent covers specific "tricks" used within the
8080 which we believed to be real inventions. b. one of these inventions was given by Ted and is the trick
for swapping the contents of registers DE and HL which you do by toggling a labelling flip/flop.
12. Ted and I had proposed a much simpler chip after our MCS-4
proposal for Busicom. This chip was called the 4005 and was to be done jointly with our Canadian parnter MIL. This chip was never built. It was to have had only 2 address registers the PC and the DataPointer. These 2 registers would be swapped to do subroutine call and save. The swap was to be done by toggling a labelling flip/flop.
13. IBM has the patent on register swap using F/F. thx. stan
------------------------------------------------- Stanley Mazor 408-542-4120 phone
Training Department 408-542-4110 fax
BEA Systems smazor@beasys.com
385 Moffett Park Dr. Enterprise Middleware
Sunnyvale, Ca. 94089-1208
______________________________________________________________________
